Memory
Addr.
Register Name
Bit 7
6
5
4
3
ELS2B
0
2
ELS2A
0
1
Bit 0
Read: CH2F
TIMA Channel 2 Status/Control
CH2IE
0
MS2B
0
MS2A
0
TOV2 CH2MAX
$0019
Register (TASC2) Write:
0
0
See page 249.
Reset:
Read:
0
0
TIMA Channel 2 Register High
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
(TACH2H) Write:
See page 252.
Reset:
Read:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
TIMA Channel 2 Register Low
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
(TACH2L) Write:
See page 252.
Reset:
Read: CH3F
0
R
0
TIMA Channel 3 Status/Control
See page 249.
CH3IE
0
MS3A
0
ELS3B
0
ELS3A
0
TOV3 CH3MAX
Register (TASC3) Write:
0
0
Reset:
Read:
0
0
TIMA Channel 3 Register High
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
(TACH3H) Write:
See page 252.
Reset:
Read:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
TIMA Channel 3 Register Low
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
(TACH3L) Write:
See page 252.
Reset:
Read:
Configuration Register
EDGE BOTNEG TOPNEG
INDEP
LVIRST
1
LVIPWR STOPE
COPD
(CONFIG) Write:
See page 80.
Reset:
0
DISX
0
0
DISY
0
0
0
PWMF
0
1
ISENS0
0
0
LDOK
0
0
Read:
PWM Control Register 1
PWMINT
ISENS1
0
PWMEN
(PCTL1) Write:
See page 158.
Reset:
Read:
0
0
0
PRSC0
0
PWM Control Register 2
LDFQ1
0
LDFQ0
0
IPOL1
0
IPOL2
0
IPOL3
0
PRSC1
0
(PCTL2) Write:
See page 160.
Reset:
Read:
0
Fault Control Register
FINT4 FMODE4
FINT3
FMODE3
FINT2
FMODE2
FINT1 FMODE1
(FCR) Write:
See page 162.
Reset:
Read: FPIN4
(FSR) Write:
0
0
0
0
0
0
0
0
FFLAG4
FPIN3
FFLAG3
FPIN2
FFLAG2
FPIN1
FFLAG1
Fault Status Register
See page 164.
Reset:
Read:
U
0
0
U
0
DT5
U
0
DT3
U
0
DT1
0
DT6
DT4
DT2
Fault Acknowledge Register
$0024
(FTACK) Write:
See page 165.
FTACK4
0
FTACK3
0
FTACK2
0
FTACK1
0
Reset:
0
0
0
0
U = Unaffected X = Indeterminate
R
= Reserved
Bold
= Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8)
Data Sheet
32
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Memory
FREESCALE [ Freescale ]
