Development Support
Monitor ROM (MON)
VDD
MC68HC908MR16/
MC68HC908MR32
10 kΩ
S1
RST
0.1 µF
VHI
10 kΩ
IRQ
VDDA
VDDA
1
20
MC145407
0.1 µF
+
+
+
+
VDDAD
10 µF
10 µF
10 µF
10 µF
VDDAD
3
4
18
17
0.1 µF
VREFH
VDD
VREFH
2
19
0.1 µF
CGMXFC
0.02 µF
10 MΩ
DB-25
2
5
6
16
15
3
7
OSC1
OSC2
X1
4.9152 MHz
20 pF
VDD
VREFL
VSSAD
VSSA
20 pF
1
2
6
4
14
3
MC74HC125
PWMGND
VSS
5
VDD
VDD
0.1 µF
VDD
7
VDD
10 kΩ
10 kΩ
PTA0
PTA7
PTC2
A
B
S3
VDD
VDD
10 kΩ
10 kΩ
S2 Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
S2 Position B — Bus clock = CGMXCLK ÷ 2
S3 Position A — Parallel communication
S3 Position B — Serial communication
A
PTC3
PTC4
S2
B
Figure 18-8. Monitor Mode Circuit
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
279
Development Support
FREESCALE [ Freescale ]
