Development Support
Break Module (BRK)
18.2.3.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break caused
an exit from wait mode. The flag is useful in applications requiring a return to wait
mode after exiting from a break interrupt.
Address:
$FE00
Bit 7
6
5
4
3
2
1
BW
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
Figure 18-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from wait mode.
Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify the
return address on the stack by subtracting 1 from it. The following code is an
example.
This code works if the H register was stacked in the break interrupt routine. Execute
this code at the end of the break interrupt routine.
HIBYTE EQU
LOBYTE EQU
5
6
; If not BW, do RTI
BRCLR
BW,BSR, RETURN
; See if wait mode or stop mode
; was exited by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
277
Development Support
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