Table 18-2. Monitor Mode Signal Requirements and Options
For Serial
Communication(2)
External
Clock(1)
RESET
(S1)
$FFFE
/$FFFF
PTC2
(S2)
Bus
Frequency
IRQ
PLL PTC3 PTC4
CGMOUT
COP
Comment
Baud
Rate(3) (4)
PTA7
(S3)
PTA0
X
GND
VDD
X
X
X
X
1
X
0
X
0
X
0
0
Disabled
Disabled
X
1
X
0
0
No operation until reset goes high
9600
PTC3 and PTC2 voltages only required if
IRQ = VTST; PTC2 determines frequency
2.4576
MHz
VTST
or
OFF
4.9152 MHz 4.9152 MHz
X
1
1
0
1
DNA
9600
DNA
VTST
divider
VDD
PTC3 and PTC2 voltages only required if
IRQ = VTST; PTC2 determines frequency
2.4576
MHz
VTST
or
X
OFF
OFF
OFF
1
X
X
0
X
X
1
X
X
9.8304 MHz 4.9152 MHz
9.8304 MHz 4.9152 MHz
Disabled
Disabled
Enabled
X
VTST
divider
1
0
1
9600
DNA
$FFFF
Blank
2.4576
MHz
VDD
VDD
VDD
External frequency always divided by 4
X
$FFFF
Blank
Enters user mode — will encounter an
illegal address reset
VTST
X
X
—
—
—
—
X
X
X
X
—
—
or
GND
VDD
VDD
Non-$FF
Programmed
or
OFF
X
X
X
Enabled
Enters user mode
or
GND
VTST
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator.
2. DNA = does not apply, X = don’t care
3. PAT0 = 1 if serial communication; PTA0 = X if parallel communication
4. PTA7 = 0 → serial, PTA7 = 1 → parallel communication for security code entry
FREESCALE [ Freescale ]
