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MC908MR32CFUE 参数 Datasheet PDF下载

MC908MR32CFUE图片预览
型号: MC908MR32CFUE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908MR32CFUE ]
分类和应用:
文件页数/大小: 308 页 / 4411 K
品牌: FREESCALE [ Freescale ]
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Development Support  
18.2.3.4 Break Flag Control Register  
The break flag control register (SBFCR) contains a bit that enables software to  
clear status bits while the MCU is in a break state.  
Address:  
$FE03  
Bit 7  
6
5
4
3
2
1
Bit 0  
R
Read:  
Write:  
Reset:  
BCFE  
R
R
R
R
R
R
0
R
= Reserved  
Figure 18-7. SIM Break Flag Control Register (SBFCR)  
BCFE — Break Clear Flag Enable Bit  
This read/write bit enables software to clear status bits by accessing status  
registers while the MCU is in a break state. To clear status bits during the break  
state, the BCFE bit must be set.  
1 = Status bits clearable during break  
0 = Status bits not clearable during break  
18.3 Monitor ROM (MON)  
The monitor ROM (MON) allows complete testing of the microcontroller unit (MCU)  
through a single-wire interface with a host computer. Monitor mode entry can be  
achieved without the use of VTST as long as vector addresses $FFFE and $FFFF  
are blank, thus reducing the hardware requirements for in-circuit programming.  
Features include:  
Normal user-mode pin functionality  
One pin dedicated to serial communication between monitor ROM and host  
computer  
Standard mark/space non-return-to-zero (NRZ) communication with host  
computer  
4800 baud–28.8 Kbaud communication with host computer  
Execution of code in random-access memory (RAM) or ROM  
FLASH programming  
18.3.1 Functional Description  
The monitor ROM receives and executes commands from a host computer.  
Figure 18-8 shows a sample circuit used to enter monitor mode and communicate  
with a host computer via a standard RS-232 interface.  
Data Sheet  
278  
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0  
Development Support  
MOTOROLA  
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