System Integration Module (SIM)
SIM Registers
14.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break
caused an exit from wait mode.
Address:
$FE00
BIt 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
Note(1)
0
R
R
R
R
R
R
R
= Reserved
Note 1. Writing a logic 0 clears SBSW.
Figure 14-14. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait mode after
exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it.
14.7.2 SIM Reset Status Register
The SIM reset status register (SRSR) contains six flags that show the source of the
last reset. Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
Address: $FE01
BIt 7
POR
R
6
5
COP
R
4
ILOP
R
3
ILAD
R
2
1
LVI
R
Bit 0
0
Read:
Write:
Reset:
PIN
MENRST
R
R
0
R
1
0
0
0
0
0
0
R
= Reserved
Figure 14-15. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA System Integration Module (SIM)
Data Sheet
207
FREESCALE [ Freescale ]
