INTERNAL BUS
M68HC08 CPU
PTA7–PTA0
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT
LOW-VOLTAGE INHIBIT
MODULE
PTB7/ATD7
PTB6/ATD6
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
COMPUTER OPERATING PROPERLY
MODULE
CONTROL AND STATUS REGISTERS — 112 BYTES
USER FLASH — 32,256 BYTES
TIMER INTERFACE
MODULE A
USER RAM — 768 BYTES
PTC6
PTC5
TIMER INTERFACE
MODULE B
PTC4
MONITOR ROM — 240 BYTES
PTC3
PTC2
SERIAL COMMUNICATIONS INTERFACE
MODULE
PTC1/ATD9(1)
PTC0/ATD8
USER FLASH VECTOR SPACE — 46 BYTES
OSC1
PTD6/IS3
CLOCK GENERATOR
MODULE
OSC2
SERIAL PERIPHERAL INTERFACE
MODULE(2)
PTD5/IS2
CGMXFC
PTD4/IS1
PTD3/FAULT4
PTD2/FAULT3
PTD1/FAULT2
PTD0/FAULT1
POWER-ON RESET
MODULE
SYSTEM INTEGRATION
MODULE
RST
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B(1)
PTE1/TCH0B(1)
PTE0/TCLKB(1)
IRQ
MODULE
IRQ
SINGLE BREAK
MODULE
VDDA
(3)
VSSA
ANALOG-TO-DIGITAL CONVERTER
MODULE
(3)
VREFL
VREFH
PTF5/TxD
PTF4/RxD
PTF3/MISO(1)
PTF2/MOSI(1)
PWMGND
PULSE-WIDTH MODULATOR
MODULE
PWM6–PWM1
PTF1/SS(1)
PTF0/SPSCK(1)
VSS
VDD
POWER
VDDAD
VSSAD
Notes:
1. These pins are not available in the 56-pin SDIP package.
2. This module is not available in the 56-pin SDIP package.
3. In the 56-pin SDIP package, these pins are bonded together.
Figure 15-1. Block Diagram Highlighting SPI Block and Pins
FREESCALE [ Freescale ]
