Serial Communications Interface Module (SCI)
Wait Mode
13.3.3.7 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive shift register
shifted in a new character before the previous character was read from the
SCDR. The previous character remains in the SCDR, and the new character
is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to
generate SCI error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming
data or break characters, including start, data, and stop bits. The noise error
interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU
interrupt requests.
•
•
Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in
SCC3 enables FE to generate SCI error CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3
enables PE to generate SCI error CPU interrupt requests.
13.4 Wait Mode
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
The SCI module remains active after the execution of a WAIT instruction. In wait
mode the SCI module registers are not accessible by the CPU. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT instruction.
13.5 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules
can be cleared during interrupts generated by the break module. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear status bits
during the break state.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write I/O registers during the break
state without affecting status bits. Some status bits have a 2-step read/write
clearing procedure. If software does the first step on such a bit before the break,
the bit cannot change during the break state as long as BCFE is at 0. After the
break, doing the second step clears the status bit.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Serial Communications Interface Module (SCI)
Data Sheet
181
FREESCALE [ Freescale ]
