Input/Output (I/O) Ports (PORTS)
Figure 10-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
PTAx
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
Figure 10-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch.
When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 10-1 summarizes the operation of the port A pins.
Table 10-1. Port A Pin Functions
Accesses to
Accesses to PTA
DDRA
Bit
DDRA
PTA Bit
I/O Pin Mode
Read/Write
DDRA[7:0]
DDRA[7:0]
Read
Pin
Write
X(1)
X
Input, Hi-Z(2)
Output
PTA[7:0](3)
PTA[7:0]
0
1
PTA[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Data Sheet
114
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Input/Output (I/O) Ports (PORTS) MOTOROLA
FREESCALE [ Freescale ]
