I/O Registers
Addr.
Register Name
Bit 7
AD9
R
6
AD8
R
5
AD7
R
4
AD6
R
3
AD5
R
2
AD4
R
1
AD3
R
Bit 0
AD2
R
Read:
Write:
Reset:
Read:
Write:
Reset:
ADC Data Register High 0
(ADRH0)
$0059
0
0
0
0
0
0
0
0
AD1
R
AD0
R
0
0
0
0
0
0
ADC Data Register Low 0
(ADRL0)
$005A
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Figure 15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode
15.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3)
The ADC data registers 1 to 3 (ADRL1–ADRL3), are 8-bit registers for conversion results in 8-bit
truncated mode, for channels ADC1 to ADC3, when the ADC is operating in auto-scan mode
(MODE[1:0] = 00).
Address: ADRL1, $005B; ADRL2, $005C; and ADRL3, $005D
Read:
Write:
Reset:
AD9
R
AD8
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-9. ADC Data Register Low 1 to 3 (ADRL1–ADRL3)
15.7.5 ADC Auto-Scan Control Register (ADASCR)
The ADC auto-scan control register (ADASCR) enables and controls the ADC auto-scan function.
Address:
Read:
$005E
0
0
0
0
0
0
0
0
AUTO1
AUTO0
0
ASCAN
0
Write:
Reset:
0
0
0
= Unimplemented
R
= Reserved
Figure 15-10. ADC Scan Control Register (ADASCR)
AUTO[1:0] — Auto-Scan Mode Channel Select Bits
AUTO1 and AUTO0 form a 2-bit field which is used to define the number of auto-scan channels used
when in auto-scan mode. Reset clears these bits.
Table 15-4. Auto-scan Mode Channel Select
AUTO1
AUTO0
Auto-Scan Channels
ADC0 only
0
0
1
1
0
1
0
1
ADC0 to ADC1
ADC0 to ADC2
ADC0 to ADC3
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
257
FREESCALE [ Freescale ]
