Analog-to-Digital Converter (ADC)
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
ADC Data Register High 0
(ADRH0)
$0059
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
AD9
R
AD8
R
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
ADC Data Register Low 0
(ADRL0)
$005A
0
0
0
0
0
0
0
0
Figure 15-5. ADRH0 and ADRL0 in 8-Bit Truncated Mode
In right justified mode the ADRH0 holds the two MSBs, and the ADRL0 holds the eight least significant
bits (LSBs), of the 10-bit result. ADRH0 and ADRL0 are updated each time a single channel ADC
conversion completes. Reading ADRH0 latches the contents of ADRL0. Until ADRL0 is read all
subsequent ADC results will be lost. (See Figure 15-6 . ADRH0 and ADRL0 in Right Justified Mode.)
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
AD9
R
Bit 0
AD8
R
Read:
Write:
Reset:
Read:
Write:
Reset:
ADC Data Register High 0
(ADRH0)
$0059
R
R
R
R
R
R
0
0
0
0
0
0
0
0
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
AD1
R
AD0
R
ADC Data Register Low 0
(ADRL0)
$005A
0
0
0
0
0
0
0
0
Figure 15-6. ADRH0 and ADRL0 in Right Justified Mode
In left justified mode the ADRH0 holds the eight most significant bits (MSBs), and the ADRL0 holds the
two least significant bits (LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each time a
single channel ADC conversion completes. Reading ADRH0 latches the contents of ADRL0. Until ADRL0
is read all subsequent ADC results will be lost. (See Figure 15-7 . ADRH0 and ADRL0 in Left Justified
Mode.)
Addr.
Register Name
Bit 7
AD9
R
6
AD8
R
5
AD7
R
4
AD6
R
3
AD5
R
2
AD4
R
1
AD3
R
Bit 0
AD2
R
Read:
Write:
Reset:
Read:
Write:
Reset:
ADC Data Register High 0
(ADRH0)
$0059
0
0
0
0
0
0
0
0
AD1
R
AD0
R
0
0
0
0
0
0
ADC Data Register Low 0
(ADRL0)
$005A
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Figure 15-7. ADRH0 and ADRL0 in Left Justified Mode
In left justified sign mode the ADRH0 holds the eight MSBs with the MSB complemented, and the ADRL0
holds the two least significant bits (LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each
time a single channel ADC conversion completes. Reading ADRH0 latches the contents of ADRL0. Until
ADRL0 is read all subsequent ADC results will be lost. (See Figure 15-8 ADRH0 and ADRL0 in Left
Justified Sign Data Mode.)
MC68HC908AP Family Data Sheet, Rev. 4
256
Freescale Semiconductor
FREESCALE [ Freescale ]
