Chapter 16
Input/Output (I/O) Ports
16.1 Introduction
Thirty-two (32) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable
as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
PTC7
PTD7
PTB6
PTC6
PTD6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002 Port C Data Register (PTC) Write:
Reset:
Read:
$0003 Port D Data Register (PTD) Write:
Reset:
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
$0004
$0005
$0006
$0007
$000C
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Data Direction Register B
(DDRB)
0
0
0
0
0
0
0
0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Data Direction Register C
(DDRC)
0
DDRD7
0
0
DDRD6
0
0
DDRD5
0
0
DDRD4
0
0
DDRD3
0
0
DDRD2
0
0
DDRD1
0
0
DDRD0
0
Data Direction Register D
(DDRD)
Port-A LED Control
LEDA7
0
LEDA6
0
LEDA5
0
LEDA4
0
LEDA3
0
LEDA2
0
LEDA1
0
LEDA0
0
Register Write:
(LEDA)
Reset:
Figure 16-1. I/O Port Register Summary
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
259
FREESCALE [ Freescale ]
