I/O Registers
15.7 I/O Registers
These I/O registers control and monitor ADC operation:
•
•
•
•
•
ADC status and control register (ADSCR) — $0057
ADC clock control register (ADICLK) — $0058
ADC data register high:low 0 (ADRH0:ADRL0) — $0059:$005A
ADC data register low 1–3 (ADRL1–ADRL3) — $005B–$005D
ADC auto-scan control register (ADASCR) — $005E
15.7.1 ADC Status and Control Register
Function of the ADC status and control register is described here.
Address:
Read:
$0057
COCO
AIEN
0
ADCO
0
ADCH4
1
ADCH3
1
ADCH2
1
ADCH1
1
ADCH0
1
Write:
Reset:
0
Figure 15-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADSCR is written, or whenever the ADC clock control
register is written, or whenever the ADC data register low, ADRLx, is read.
If the AIEN bit is logic 1, the COCO bit always read as logic 0. ADC interrupt will be generated at the
end if an ADC conversion. Reset clears the COCO bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register, ADR0, is read or the ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADC data register at the end of
each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
This bit should not be set when auto-scan mode is enabled; i.e. when ASCAN=1.
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels when not in auto-scan
mode. The five channel select bits are detailed in Table 15-1.
NOTE
Care should be taken when using a port pin as both an analog and a digital
input simultaneously to prevent switching noise from corrupting the analog
signal. Recovery from the disabled state requires one conversion cycle to
stabilize.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
253
FREESCALE [ Freescale ]
