I/O Registers
Table 15-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at f
, correct operation can be guaranteed.
ADIC
1 = Internal bus clock
0 = External clock, CGMXCLK
CGMXCLK or bus frequency
ADIV[2:0]
f
=
ADIC
MODE1 and MODE0 — Modes of Result Justification
MODE1 and MODE0 selects between four modes of operation. The manner in which the ADC
conversion results will be placed in the ADC data registers is controlled by these modes of operation.
Reset returns right-justified mode.
Table 15-3. ADC Mode Select
MODE1
MODE0
Justification Mode
8-bit truncated mode
0
0
1
1
0
1
0
1
Right justified mode
Left justified mode
Left justified sign data mode
15.7.3 ADC Data Register 0 (ADRH0 and ADRL0)
The ADC data register 0 consist of a pair of 8-bit registers: high byte (ADRH0), and low byte (ADRL0).
This pair form a 16-bit register to store the 10-bit ADC result for the selected ADC result justification mode.
In 8-bit truncated mode, the ADRL0 holds the eight most significant bits (MSBs) of the 10-bit result. The
ADRL0 is updated each time an ADC conversion completes. In 8-bit truncated mode, ADRL0 contains no
interlocking with ADRH0. (See Figure 15-5 . ADRH0 and ADRL0 in 8-Bit Truncated Mode.)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
255
FREESCALE [ Freescale ]
