Input/Output (I/O) Ports
Table 16-1. Port Control Register Bits Summary
Module Control
Port
Bit
DDR
Pin
Module
Register
Control Bit
0
1
2
3
4
5
6
7
0
DDRA0
DDRA1
DDRA2
DDRA3
DDRA4
DDRA5
DDRA6
DDRA7
DDRB0
PTA0/ADC0
PTA1/ADC1
PTA2/ADC2
PTA3/ADC3
PTA4/ADC4
PTA5/ADC5
PTA6/ADC6
PTA7/ADC7
A
ADC
ADSCR ($0057)
ADCH[4:0]
PTB0/SDA(1)
PTB1/SCL(1)
MBUS
SCI
MMCR1 ($0049)
SCC1 ($0013)
MMEN
ENSCI
1
2
3
4
5
6
7
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
DDRB6
DDRB7
PTB2/TxD(1)
PTB3/RxD(1)
B
PTB4/T1CH0(2)
PTB5/T1CH1(2)
PTB6/T2CH0(2)
PTB7/T2CH1(2)
T1SC0 ($0025)
T1SC1 ($0028)
T2SC0 ($0030)
T2SC1 ($0033)
INTSCR2 ($001C)
—
ELS0B:ELS0A
ELS1B:ELS1A
ELS0B:ELS0A
ELS1B:ELS1A
IMASK2
TIM1
TIM2
PTC0/IRQ2(2)
PTC1
0
1
2
3
4
5
6
DDRC0
DDRC1
DDRC2
DDRC3
DDRC4
DDRC5
DDRC6
IRQ2
—
—
PTC2/MISO
PTC3/MOSI
PTC4/SS
SPI
SPCR ($0010)
SPE
C
PTC5/SPSCK
PTC6/SCTxD(1)
IRSCI
IRSCC1 ($0040)
ENSCI
PTC7/SCRxD(1)
PTD0/KBI0(2)
PTD1/KBI1(2)
PTD2/KBI2(2)
PTD3/KBI3(2)
PTD4/KBI4(2)
PTD5/KBI5(2)
PTD6/KBI6(2)
PTD7/KBI7(2)
7
0
1
2
3
4
5
6
7
DDRC7
DDRD0
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRD7
KBIE0
KBIE1
KBIE2
KBIE3
KBIE4
KBIE5
KBIE6
KBIE7
D
KBI
KBIER ($001B)
1. Pin is open-drain when configured as output. Pullup resistor must be connected when configured as output.
2. Pin has schmitt trigger when configured as input.
MC68HC908AP Family Data Sheet, Rev. 4
260
Freescale Semiconductor
FREESCALE [ Freescale ]
