Analog-to-Digital Converter (ADC)
Table 15-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
ADC0
Input Select
PTA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC1
PTA1
ADC2
PTA2
ADC3
PTA3
ADC4
PTA4
ADC5
PTA5
ADC6
PTA6
ADC7
PTA7
0
↓
1
1
↓
1
0
↓
1
0
↓
0
0
↓
0
ADC8
↓
ADC28
Reserved
VREFH (see Note 2)
VREFL (see Note 2)
—
1
1
1
1
1
1
1
0
1
1
1
0
1
ADC29
ADC30
1
1
ADC powered-off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of
the ADC converter both in production test and for user applications.
15.7.2 ADC Clock Control Register
The ADC clock control register (ADICLK) selects the clock frequency for the ADC.
Address:
Read:
$0058
ADIV2
0
0
0
0
R
0
ADIV1
0
ADIV0
0
ADICLK
0
MODE1
MODE0
Write:
Reset:
0
1
= Unimplemented
R
= Reserved
Figure 15-4. ADC Clock Control Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
Table 15-2 shows the available clock configurations. The ADC clock should be set to between 500 kHz
and 1MHz.
MC68HC908AP Family Data Sheet, Rev. 4
254
Freescale Semiconductor
FREESCALE [ Freescale ]
