Multi-Master IIC Interface (MMIIC)
Under normal operation, the user software should clear MMTXAK bit before setting MMCRCBYTE bit
to ensure that an acknowledge signal is sent when no CRC error is detected.
The MMCRCBYTE bit should not be set in transmit mode. This bit is cleared by the next START signal.
Reset also clears this bit.
1 = Next receiving byte is the packet error checking (PEC) data
0 = Next receiving byte is not PEC data
14.6.3 MMIIC Control Register 2 (MMCR2)
Address:
$004A
Bit 7
6
5
4
MMAST
0
3
MMRW
0
2
0
1
0
Bit 0
Read: MMALIF MMNAKIF
MMBB
MMCRCEF
Unaffected
Write:
0
0
0
0
Reset:
0
0
0
= Unimplemented
Figure 14-6. MMIIC Control Register 2 (MMCR2)
MMALIF — Arbitration Loss Interrupt Flag
This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start
condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode — an arbitration loss. This bit generates an interrupt request to the CPU if the
MMIEN bit in MMCR1 is set. This bit is cleared by writing "0" to it or by reset.
1 = Lost arbitration in master mode
0 = No arbitration lost
MMNAKIF — No AcKnowledge Interrupt Flag (Master Mode)
This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one
data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR1 is set. This bit is cleared by writing "0" to it or by
reset.
1 = No acknowledge bit detected
0 = Acknowledge bit detected
MMBB — MMIIC Bus Busy Flag
This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus
idle) is detected or the MMIIC is disabled. Reset clears this bit.
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
MMAST — MMIIC Master Control
This bit is set to initiate a master mode transfer. In master mode, the module generates a start
condition to the SDA and SCL lines, followed by sending the calling address stored in MMADR.
When the MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module
generates the stop condition to the lines after the current byte is transmitted.
If an arbitration loss occurs (MMALIF = 1), the module reverts to slave mode by clearing MMAST, and
releasing SDA and SCL lines immediately.
This bit is cleared by writing "0" to it or by reset.
1 = Master mode operation
0 = Slave mode operation
MC68HC908AP Family Data Sheet, Rev. 4
236
Freescale Semiconductor
FREESCALE [ Freescale ]
