Multi-Master IIC Interface (MMIIC)
MMSRW — MMIIC Slave Read/Write Select
This bit indicates the data direction when the module is in slave mode. It is updated after the calling
address is received from a master device. MMSRW = 1 when the calling master is reading data from
the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive
mode).
1 = Slave mode transmit
0 = Slave mode receive
MMRXAK — MMIIC Receive Acknowledge
When this bit is cleared, it indicates an acknowledge signal has been received after the completion of
eight data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has
been detected at the 9th clock; the module will release the SDA line for the master to generate STOP
or repeated START condition. Reset sets this bit.
1 = No acknowledge signal received at 9th clock
0 = Acknowledge signal received at 9th clock
MMCRCBF — CRC Data Buffer Full Flag
This flag is set when the CRC data register (MMCRCDR) is loaded with a CRC byte for the current
received or transmitted data.
In transmit mode, after a byte of data has been sent (MMTXIF = 1), the MMCRCBF will be set when
the CRC byte has been generated and ready in the MMCRCDR. The content of the MMCRCDR should
be copied to the MMDTR for transmission.
In receive mode, the MMCRCBF is set when the CRC byte has been generated and ready in
MMCRCDR, for the current byte of received data.
The MMCRCBF bit is cleared when the CRC data register is read. Reset also clears this bit.
1 = Data ready in CRC data register (MMCRCDR)
0 = Data not ready in CRC data register (MMCRCDR)
MMTXBE — MMIIC Transmit Buffer Empty
This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to
the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer
of its data to the output circuit. Reset sets this bit.
1 = Data transmit register empty
0 = Data transmit register full
MMRXBF — MMIIC Receive Buffer Full
This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data
from the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer
of data from the input circuit to the MMDRR. Reset clears this bit.
1 = Data receive register full
0 = Data receive register empty
14.6.5 MMIIC Data Transmit Register (MMDTR)
Address:
$004C
Bit 7
6
MMTD6
0
5
MMTD5
0
4
MMTD4
0
3
MMTD3
0
2
MMTD2
0
1
MMTD1
0
Bit 0
MMTD0
0
Read:
Write:
Reset:
MMTD7
0
Figure 14-8. MMIIC Data Transmit Register (MMDTR)
MC68HC908AP Family Data Sheet, Rev. 4
238
Freescale Semiconductor
FREESCALE [ Freescale ]
