MMIIC I/O Registers
When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit when:
•
the module detects a matched calling address (MMATCH = 1), with the calling master requesting
data (MMSRW = 1); or
•
the previous data in the output circuit has be transmitted and the receiving master returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA
line for master to generate a STOP or repeated START condition. The data in the MMDTR will not be
transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains
cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output circuit when:
•
the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or
the previous data in the output circuit has be transmitted and the receiving slave returns an
acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0).
•
If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a STOP or
repeated START condition. The data in the MMDTR will not be transferred to the output circuit. The
transmit buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are illustrated in Figure 14-12.
14.6.6 MMIIC Data Receive Register (MMDRR)
Address:
$004D
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRD7
Write:
MMRD6
MMRD5
MMRD4
MMRD3
MMRD2
MMRD1
MMRD0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-9. MMIIC Data Receive Register (MMDRR)
When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether
module is in master or slave mode.
In slave mode, the data in MMDRR is:
•
•
the calling address from the master when the address match flag is set (MMATCH = 1); or
the last data received when MMATCH = 0.
In master mode, the data in the MMDRR is:
the last data received.
•
When the MMDRR is read by the CPU, the receive buffer full flag is cleared (MMRXBF = 0), and the next
received data is loaded to the MMDRR. Each time when new data is loaded to the MMDRR, the MMRXIF
interrupt flag is set, indicating that new data is available in MMDRR.
The sequence of events for slave receive and master receive are illustrated in Figure 14-12.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
239
FREESCALE [ Freescale ]
