Multi-Master IIC Interface (MMIIC)
14.6.1 MMIIC Address Register (MMADR)
Address:
$0048
Bit 7
6
MMAD6
0
5
MMAD5
1
4
MMAD4
0
3
MMAD3
0
2
MMAD2
0
1
Bit 0
Read:
Write:
Reset:
MMAD7
1
MMAD1 MMEXTAD
0
0
Figure 14-4. MMIIC Address Register (MMADR)
MMAD[7:1] — Multi-Master Address
These seven bits represent the MMIIC interface’s own specific slave address when in slave mode, and
the calling address when in master mode. Software must update MMAD[7:1] as the calling address
while entering master mode and restore its own slave address after master mode is relinquished. This
register is cleared as $A0 upon reset.
MMEXTAD — Multi-Master Expanded Address
This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will
acknowledge the following addresses from a calling master: $MMAD[7:1], 0000000, and 0001100.
Reset clears this bit.
1 = MMIIC responds to the following calling addresses:
$MMAD[7:1], 0000000, and 0001100.
0 = MMIIC responds to address $MMAD[7:1]
For example, when MMADR is configured as:
MMAD7
1
MMAD6
1
MMAD5
0
MMAD4
1
MMAD3
0
MMAD2
1
MMAD1 MMEXTAD
0
1
The MMIIC module will respond to the calling address:
Bit 7
1
6
1
5
0
4
1
3
0
2
1
Bit 1
0
or the general calling address:
0
0
0
0
0
0
0
or the calling address:
Bit 7
0
6
0
5
0
4
1
3
1
2
0
Bit 1
0
Note that bit-0 of the 8-bit calling address is the MMRW bit from the calling master.
MC68HC908AP Family Data Sheet, Rev. 4
234
Freescale Semiconductor
FREESCALE [ Freescale ]
