MMIIC I/O Registers
in this device clock may not change the state of the SCL line if another device clock is still in its low period.
Therefore the synchronized clock SCL will be held low by the device which last releases SCL to logic high.
Devices with shorter low periods enter a high wait state during this time. When all devices concerned have
counted off their low period, the synchronized SCL line will be released and go high, and all devices will
start counting their high periods. The first device to complete its high period will again pull the SCL line
low. Figure 14-3 illustrates the clock synchronization waveforms.
Start counting high period
WAIT
SCL1
SCL2
SCL
Internal counter reset
Figure 14-3. Clock Synchronization
14.5.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. A slave device may
hold the SCL low after completion of one byte data transfer and will halt the bus clock, forcing the master
clock into a wait state until the slave releases the SCL line.
14.5.9 Packet Error Code
The packet error code (PEC) for the MMIIC interface is in the form a cyclic redundancy code (CRC). The
PEC is generated by hardware for every transmitted and received byte of data. The transmission of the
generated PEC is controlled by user software.
The CRC data register, MMCRCDR, contains the generated PEC byte, with three other bits in the MMIIC
control registers and status register monitoring and controlling the PEC byte.
14.6 MMIIC I/O Registers
These I/O registers control and monitor MMIIC operation:
•
•
•
•
•
•
•
•
MMIIC address register (MMADR) — $0048
MMIIC control register 1 (MMCR1) — $0049
MMIIC control register 2 (MMCR2) — $004A
MMIIC status register (MMSR) — $004B
MMIIC data transmit register (MMDTR) — $004C
MMIIC data receive register (MMDRR) — $004D
MMIIC CRC data register (MMCRCDR) — $004E
MMIIC frequency divide register (MMFDR) — $004F
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
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FREESCALE [ Freescale ]
