Multi-Master IIC Interface (MMIIC)
14.6.7 MMIIC CRC Data Register (MMCRCDR)
Address:
$004E
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-10. MMIIC CRC Data Register (MMCRCDR)
When the MMIIC module is enabled, MMEN = 1, and the CRC buffer full flag is set (MMCRCBF = 1), data
in this read-only register contains the generated CRC byte for the last byte of received or transmitted data.
A CRC byte is generated for each received and transmitted data byte and loaded to the CRC data
register. The MMCRCBF bit will be set to indicate the CRC byte is ready in the CRC data register.
Reading the CRC data register clears the MMCRCBF bit. If the CRC data register is not read, the
MMCRCBF bit will be cleared by hardware before the next CRC byte is loaded.
14.6.8 MMIIC Frequency Divider Register (MMFDR)
Address:
$004F
Bit 7
0
6
0
5
0
4
0
3
0
2
MMBR2
1
1
MMBR1
0
Bit 0
MMBR0
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 14-11. MMIIC Frequency Divider Register (MMFDR)
The three bits in the frequency divider register (MMFDR) selects the divider to divide the bus clock to the
desired baud rate for the MMIIC data transfer.
Table 14-2 shows the divider values for MMBR[2:0].
MC68HC908AP Family Data Sheet, Rev. 4
240
Freescale Semiconductor
FREESCALE [ Freescale ]
