Multi-Master IIC Interface (MMIIC)
Only the slave with a matched address will respond by sending back an acknowledge bit by pulling SDA
low on the 9th clock cycle.
(See Figure 14-2.)
14.5.3 Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the
direction specified by the R/W-bit sent by the calling master.
Each data byte is 8 bits. Data can be changed only when SCL is low and must be held stable when SCL
is high as shown in Figure 14-2. The MSB is transmitted first and each byte has to be followed by an
acknowledge bit. This is signalled by the receiving device by pulling the SDA low on the 9th clock cycle.
Therefore, one complete data byte transfer requires 9 clock cycles.
If the slave receiver does not acknowledge the master, the SDA line should be left high by the slave. The
master can then generate a STOP signal to abort the data transfer or a START signal (repeated START)
to commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it
means an “end of data” to the slave. The slave should release the SDA line for the master to generate a
STOP or START signal.
14.5.4 Repeated START Signal
As shown in Figure 14-2, a repeated START signal is used to generate START signal without first
generating a STOP to terminate the communication. This is used by the master to communicate with
another slave or with the same slave in a different mode (transmit/receive mode) without releasing the
bus.
14.5.5 STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without first generating a STOP
signal. This is called repeat START. A STOP signal is defined as a low to high transition of SDA while
SCL is at logic high (see Figure 14-2).
14.5.6 Arbitration Procedure
The interface circuit is a multi-master system which allows more than one master to be connected. If two
or more masters try to control the bus at the same time, a clock synchronization procedure determines
the bus clock. The clock low period is equal to the longest clock low period and the clock high period is
equal to the shortest one among the masters. A data arbitration procedure determines the priority. A
master will lose arbitration if it transmits a logic 1 while another transmits a logic 0. The losing master will
immediately switch over to slave receive mode and stops its data and clock outputs. The transition from
master to slave will not generate a STOP condition. Meanwhile a software bit will be set by hardware to
indicates loss of arbitration.
14.5.7 Clock Synchronization
Since wired-AND logic is performed on SCL line, a high to low transition on the SCL line will affect the
devices connected to the bus. The devices start counting their low period once a device’s clock has gone
low, it will hold the SCL line low until the clock high state is reached. However, the change of low to high
MC68HC908AP Family Data Sheet, Rev. 4
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Freescale Semiconductor
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