General Parameters
Table 1. Microarchitecture Comparison (continued)
MPC7450/MPC7451/
Microarchitectural Specs
MPC7455/MPC7445
MPC7400/MPC7410
MPC7441
Cache level
L2
L2
256-Kbyte/8-Way
256 Bits
L2 tags and controller
only (see off-chip cache
support below)
Size/associativity
Access width
256-Kbyte/8-Way
256 Bits
2
Number of 32-byte sectors/line
Parity
2
Byte
Byte
2
Off-Chip Cache Support
Cache level
L3
1MB, 2MB
8-Way
2, 4
L3
1MB, 2MB
8-Way
2, 4
L2
0.5MB, 1MB, 2MB
2-Way
On-chip tag logical size
Associativity
Number of 32-byte sectors/line
Off-chip data SRAM support
Data path width
1, 2, 4
MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2
LW, PB2, PB3
64
64
64
Direct mapped SRAM sizes
1 Mbyte, 2 Mbytes
1 Mbyte, 2 Mbytes
0.5 Mbyte, 1 Mbyte,
3
2 Mbytes
Parity
Byte
Byte
Byte
Notes:
1. Numbers in parentheses are for 2:1 SRAM.
2. Not implemented on MPC7445 or MPC7441.
3. Private memory feature not implemented on MPC7400.
4 General Parameters
The following list provides a summary of the general parameters of the MPC7455:
Technology
Die size
0.18 µm CMOS, six-layer metal
2
8.69 mm × 12.17 mm (106 mm )
Transistor count
Logic design
Packages
33 million
Fully-static
MPC7445: Surface mount 360 ceramic ball grid array (CBGA)
MPC7455: Surface mount 483 ceramic ball grid array (CBGA)
Core power supply
1.3 V ± 50 mV DC nominal
1.8 V ± 5% DC, or
I/O power supply
2.5 V ± 5% DC, or
1.5 V ± 5% DC (L3 interface only)
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
9
FREESCALE [ Freescale ]
