Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
Table 1. Microarchitecture Comparison (continued)
MPC7450/MPC7451/
Microarchitectural Specs
MPC7455/MPC7445
MPC7400/MPC7410
MPC7441
Scalar floating-point unit
In Order
In Order
In Order
Branch Processing Resources
Prediction structures
BTIC, BHT, Link Stack BTIC, BHT, Link Stack
BTIC, BHT
BTIC size, associativity
BHT size
128-Entry, 4-Way
128-Entry, 4-Way
64-Entry, 4-Way
2K-Entry
2K-Entry
512-Entry
Link stack depth
8
3
1
6
8
3
1
6
None
Unresolved branches supported
Branch taken penalty (BTIC hit)
Minimum misprediction penalty
2
0
4
Execution Unit Timings (Latency-Throughput)
Aligned load (integer, float, vector)
Misaligned load (integer, float, vector)
L1 miss, L2 hit latency
3-1, 4-1, 3-1
3-1, 4-1, 3-1
2-1, 2-1, 2-1
3-2, 3-2, 3-2
4-2, 5-2, 4-2
4-2, 5-2, 4-2
1
9 Data/13 Instruction
9 Data/13 Instruction
9 (11)
SFX (aDd Sub, Shift, Rot, Cmp, logicals)
Integer multiply (32 × 8, 32 × 16, 32 × 32)
Scalar float
1-1
3-1, 3-1, 4-2
5-1
1-1
3-1, 3-1, 4-2
5-1
1-1
2-1, 3-2, 5-4
3-1
VSFX (vector simple)
1-1
1-1
1-1
VCFX (vector complex)
4-1
4-1
3-1
VFPU (vector float)
4-1
4-1
4-1
VPER (vector permute)
2-1
2-1
1-1
MMUs
TLBs (instruction and data)
Tablewalk mechanism
128-Entry, 2-Way
Hardware + Software
8/8
128-Entry, 2-Way
Hardware + Software
4/4
128-Entry, 2-Way
Hardware
4/4
Instruction BATs/data BATs
L1 I Cache/D Cache Features
Size
32K/32K
8-Way
Way
32K/32K
8-Way
Way
32K/32K
8-Way
Associativity
Locking granularity
Parity on I cache
Full Cache
None
Word
Word
Parity on D cache
Number of D cache misses (load/store)
Data stream touch engines
Byte
Byte
None
5/1
5/1
8 (Any Combination)
4 Streams
4 Streams
4 Streams
On-Chip Cache Features
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
8
Freescale Semiconductor
FREESCALE [ Freescale ]
