Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
System initialization
$x000
$x07F
$x080
$x000
$x07F
$x080
RAM A
RAM B
Register block
RAM B
RAM A
$x3FF
$x3FF
$x400
$x47F
Register and RAM mapped
to different 4k boundaries.
Register and RAM mapped
to the same 4k boundary.
Figure 3-2. RAM and register overlap
3.5.2.3 INIT2 — EEPROM mapping and MI BUS delay register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EEPROM mapping (INIT2)
$0037 EE3 EE2 EE1 EE0 M3DL1M3DL0M2DL1M2DL00000 0000
This register determines the location of EEPROM in the memory map.
INIT2 may be read at any time but bits 7–4 may be written only once after
reset in normal modes (bits 3–0 may be written at any time).
EE[3:0] — EEPROM map position
EEPROM is located at $xD80–$xFFF, where x is the hexadecimal
digit represented by EE[3:0]. Refer to Table 3-6.
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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