Freescale Semiconductor, Inc.
Pin Descriptions
MODA and MODB (MODA/LIR and MODB/VSTBY)
2.10 MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes.
Refer to Operating Modes and On-Chip Memory.
After the operating mode has been selected, the LIR pin provides an
open-drain output to indicate that execution of an instruction has begun.
The LIR pin is normally configured for wired-OR operation (only pulls
low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a short time to
prevent false triggering. A series of E clock cycles occurs during
execution of each instruction. The LIR signal goes low during the first E
clock cycle of each instruction (opcode fetch). This output is provided for
assistance in program debugging and its operation is controlled by the
LIRDV bit in the OPT2 register.
The VSTBY pin is used to input RAM stand-by power. The MCU is
powered from the VDD pin unless the difference between the level of
VSTBY and VDD is greater than one MOS threshold (about 0.7 volts).
When these voltages differ by more than 0.7 volts, the internal 1024-byte
RAM and part of the reset logic are powered from VSTBY rather than
VDD. This allows RAM contents to be retained without VDD power
applied to the MCU. Reset must be driven low before VDD is removed
and must remain low until VDD has been restored to a valid level.
V
4.7k¾
DD
To MODB/VSTBY
pin of M68HC11
V
V
OUT
DD
4.8 V NiCd
MAX 690
(+)
V
BATT
Figure 2-5. RAM stand-by connections
MC68HC11P2 — Rev 1.0
Technical Data
Pin Descriptions
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