Freescale Semiconductor, Inc.
Pin Descriptions
outputs. Writes to PORTA do not change the pin state when the pins are
configured for timer output compares.
Out of reset, port A pins [7:0] are general-purpose high-impedance
inputs. When the functions associated with these pins are disabled, the
bits in DDRA govern the I/O state of the associated pin. For further
information, refer to Parallel Input/Output.
2.13.2 Port B
Port B is an 8-bit general-purpose I/O port with a data register (PORTB)
and a data direction register (DDRB). In single chip mode, port B pins are
general-purpose I/O pins (PB[7:0]). In expanded mode, port B pins act
as the high-order address lines (A[15:8]) of the address bus.
PORTB can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTB is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. For further information, refer to
Parallel Input/Output.
Port B pins include on-chip pull-up devices which can be enabled or
disabled.
2.13.3 Port C
Port C is an 8-bit general-purpose I/O port with a data register (PORTC)
and a data direction register (DDRC). In single chip mode, port C pins
are general-purpose I/O pins (PC[7:0]). In the expanded mode, port C
pins are configured as data bus pins (D[7:0]).
PORTC can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTC is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. Port C pins are general-
purpose inputs out of reset in single chip and bootstrap modes. In
expanded and test modes, these pins are data bus lines out of reset.
Technical Data
MC68HC11P2 — Rev 1.0
Pin Descriptions
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