Freescale Semiconductor, Inc.
Pin Descriptions
the PLL is near the specified frequency. The high bandwidth driver is
then disabled and BWC is cleared by internal circuitry. Reset clears
this bit.
High
bandwidth
Auto
BWC
0
0
1
0
1
X
Off
On
Auto
VCOT — VCO test (Test mode only)
1 = Loop filter operates as specified by AUTO and BWC.
0 = Low bandwidth mode of the PLL filter is disabled.
This bit is used to isolate the loop filter from the VCO for testing
purposes. VCOT is always set when AUTO = 1 when running in
automatic mode. This bit is writable only in test mode. Reset sets this
bit.
MCS — Module clock select
1 = 4XCLK is the source for the SCI and timer divider chain.
0 = EXTAL is the source for the SCI and timer divider chain.
Reset clears this bit.
LCK — Synthesizer lock detect
1 = The PLL has stabilized.
0 = The PLL is not stable.
This bit is used as an indicator for software that it is all right to set
BCS.
WEN — WAIT enable
1 = Low-power WAIT mode selected (PLL set to ‘idle’ in WAIT
mode).
0 = Do not alter the 4XCLK during WAIT mode.
This bit determines whether the 4XCLK is disconnected from
VCOOUT during WAIT and connected to EXTAL. Reset clears this
bit.
When set, the CPU will respond to a WAIT instruction by first stacking
Technical Data
MC68HC11P2 — Rev 1.0
Pin Descriptions
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