Freescale Semiconductor, Inc.
Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
Any interrupt, any reset, or the assertion of RAF in any of the SCIs will
allow the PLL to resume operating at the frequency specified in the
SYNR. The user must set BCS after the PLL has had time to adjust
(tPLLS). If, for a specific SCI, the RE bit is clear, then RAF cannot
become set, hence the PLL will not resume normal operation.
2.7.3.2 SYNR — Synthesizer program register
State
on reset
Address bit 7 bit 6 bit 5
bit 4 bit 3 bit 2
bit 1 bit 0
Synthesizer program (SYNR)
$002F SYNX1SYNX0SYNY5SYNY4SYNY3SYNY2SYNY1SYNY0 0000 1011
The PLL frequency synthesizer multiplies the frequency of the crystal
oscillator. The multiplication factor is software programmable via a loop
divider, which consists of a six-bit modulo N counter, with a further two
bit scaling factor.
The multiplication factor is given by 2(Y + 1)2X, where 0 ð X ð 3 and 0 ð
Y ð 63.
NOTE: Exceeding recommended operating frequencies can result in
indeterminate MCU operation.
SYNX[1:0]
These bits program the binary taps (divide by 1, 2, 4 and 8). Reset
clears these bits.
SYNY[5:0]
These bits program the six-bit modulo N (1 to 64) counter. Reset sets
these bits to %001011.
NOTE: The resolution of the multiplication factors decreases by a factor of two,
as X increases:
X
0
1
2
3
Y
Possible multipliers
2, 4, 6, 8, …, 128
0 – 63
0 – 63
0 – 63
0 – 63
4, 8, 12, 16, …, 256
8, 16, 24, 32, …, 512
16, 32, 48, 64, …, 1024
MC68HC11P2 — Rev 1.0
Technical Data
Pin Descriptions
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