Freescale Semiconductor, Inc.
Pin Descriptions
Port signals
The CWOM control bit in the OPT2 register disables port C’s P-channel
output drivers. Because the N-channel driver is not affected by CWOM,
setting CWOM causes port C to become an open-drain-type output port
suitable for wired-OR operation. In wired-OR mode (PORTC bits at logic
level zero), the pins are actively driven low by the N-channel driver.
When a port C bit is at logic level one, the associated pin is in a high
impedance state as neither the N-channel nor the P-channel devices are
active. It is customary to have an external pull-up resistor on lines that
are driven by open-drain devices. Port C can only be configured for
wired-OR operation when the MCU is in single chip mode. For further
information, refer to Parallel Input/Output.
2.13.4 Port D
Port D, a 6-bit general-purpose I/O port, has a data register (PORTD)
and a data direction register (DDRD). The six port D lines (D[5:0]) can
be used for general-purpose I/O, for one of the serial communications
interfaces (SCI1, bits [0:1]) and for the serial peripheral interface (SPI,
bits [2:5]) subsystem.
PORTD can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTD is written, the data is stored in
internal latches and are driven only if port D is configured for general-
purpose output.
For further information, refer to Parallel Input/Output, Serial
Communications Interface (SCI) and Serial Peripheral Interface
(SPI).
2.13.5 Port E
Port E, PE/AD[7:0], is an input-only port that can also be used as the
analog inputs for the analog-to-digital converter.
For further information, refer to Parallel Input/Output and Analog-to-
Digital Converter.
MC68HC11P2 — Rev 1.0
Technical Data
Pin Descriptions
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