Freescale Semiconductor, Inc.
Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the circuit to stabilize before it drives the
CPU clocks. PLLON is set by reset, to allow the control loop to
stabilize during power up.
PLLON cannot be cleared whilst using VCOOUT to drive the internal
processor clock, i.e. when BCS is set.
BCS — Bus clock select
1 = VCOOUT output drives the clock circuit (4XCLK).
0 = EXTAL drives the clock circuit (4XCLK).
This bit determines which signal drives the clock circuit generating the
bus clocks. Once BCS has been altered it can take up to [1.5 EXTAL
+ 1.5 VCOOUT] cycles for the change in the clock to occur. Reset
clears this bit.
NOTE: PLLON and BCS have built-in safeguards so that VCOOUT cannot be
selected as the clock source (BCS = 1) if the PLL is off (PLLON = 0).
Similarly, the PLL cannot be turned off (PLLON = 0) if it is on and in use
(BCS = 1). Turning the PLL on and selecting VCOOUT as the clock
source therefore requires two independent writes to PLLCR.
AUTO — Automatic bandwidth control
1 = Automatic bandwidth control selected.
0 = Manual bandwidth control selected.
AUTO selects between automatic bandwidth control circuits in the
phase detect block and manual bandwidth control. Reset sets this bit.
BWC — Bandwidth control
1 = High bandwidth control selected.
0 = Low bandwidth control selected.
Bandwidth control is under manual control only when AUTO is clear.
(When AUTO is set, BWC acts as a read-only status bit to indicate
which mode has been selected by the internal circuit.) A delay of tPLLS
is required between changes to BWC. The low bandwidth driver is
always enabled, so this bit determines whether the high bandwidth
driver is on or off. On PLL start-up in automatic mode (AUTO = 1), the
high bandwidth driver is enabled (BWC = 1) by internal circuitry until
MC68HC11P2 — Rev 1.0
Technical Data
Pin Descriptions
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