Freescale Semiconductor, Inc.
Pin Descriptions
2.7.2 Changing the PLL frequency
To change the PLL frequency it is necessary to perform the following
sequence of events, in order to prevent possible bursts of high frequency
operation during the reconfiguration of the PLL:
1. Switch to the low frequency bus rate (BCS = 0)
2. Disable the PLL (PLLON = 0)
3. Change the value in SYNR
4. Enable the PLL (PLLON = 1)
5. Wait a time tPLLS for the PLL frequency to stabilize
6. Switch to the high frequency bus rate (BCS = 1)
2.7.3 PLL registers
Two registers are used to control the operation of the MC68HC11P2
phase-locked loop circuitry. These are the PLL control register and the
synthesizer program register, each of which is described below.
2.7.3.1 PLLCR — PLL control register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PLL control (PLLCR)
$002E PLLON BCS AUTO BWC VCOT MCS LCK WEN 1010 1000
This read/write register contains two bits that are used to enable and
disable the synthesizer and to switch from slow (EXTAL) to one of the
fast speeds. Two further bits are used to control the filter bandwidth. The
SCI and timer clock source and the slow clock for WAIT mode are also
controlled by this register.
PLLON — PLL on
1 = Switch PLL on.
0 = Switch PLL off.
Technical Data
MC68HC11P2 — Rev 1.0
Pin Descriptions
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