Freescale Semiconductor, Inc.
Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
The PLL filter has two bandwidths that are automatically selected by the
PLL, if the AUTO bit in PLLCR is set. Whenever the PLL is first enabled,
the wide bandwidth mode is used. This enables the PLL frequency to
ramp up quickly. When the output frequency is near the desired value,
the filter is switched to the narrow bandwidth mode, to make the final
frequency more stable. Manual control is possible, by clearing AUTO in
PLLCR, and setting the appropriate value for BWC.
A block diagram of the PLL circuitry is given in Figure 2-4.
V
DDSYN
EXTAL
XFC
4XCLK
Bus clock
select
t
REF
Phase
detect
PCOMP
Loop filter
VCO
To clock
generation
circuitry
EXTAL
Low frequency
crystal oscillator
BCS
ST4XCK
t
FB
VCOOUT
Module clock
Frequency divider
SYNR
select
For SCI
and timer
EXTAL
MCS
Figure 2-4. PLL circuit
2.7.1 Synchronization of PLL with subsystems
The timer and SCI subsystems operate off the EXTAL clock, but are
accessed by the CPU relative to the internal PH2 signal. Although the
EXTAL clock is used as the reference for the PLL, the PH2 clock and the
module clocks for the timer and the SCI are not synchronized. In order
MC68HC11P2 — Rev 1.0
Technical Data
Pin Descriptions
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
