Freescale Semiconductor, Inc.
Pin Descriptions
V
DD
V
DD
2
4.7 k¾
IN
1
To M68HC11
RESET
RESET
MC34064
GND
3
V
DD
Manual
reset
4.7 k¾
2
4.7 k¾
1µF
IN
1
RESET
MC34164
GND
3
Figure 2-2. External reset circuitry
2.5 Crystal driver and external clock input (XTAL, EXTAL)
These two pins provide the interface for either a crystal or a CMOS
compatible clock to control the internal clock generator circuitry. The
frequency applied to these pins must be four times higher than the
desired E clock rate (unless the PLL circuit is used to provide the E
clock).
The XTAL pin is normally left unconnected when an external CMOS
compatible clock input is connected to the EXTAL pin. However, a 10 k¾
to 100 k¾ load resistor connected from XTAL to ground can be used to
reduce RFI noise emission. The XTAL output is normally intended to
drive only a crystal. The XTAL output can be buffered with a high-
impedance buffer, or it can be used to drive the EXTAL input of another
M68HC11 family device.
Technical Data
MC68HC11P2 — Rev 1.0
Pin Descriptions
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