Freescale Semiconductor, Inc.
Timing System
8.6 Real-time interrupt
The real-time interrupt (RTI) feature, used to generate hardware
interrupts at a fixed periodic rate, is controlled and configured by two bits
(RTR1 and RTR0) in the pulse accumulator control (PACTL) register.
The RTII bit in the TMSK2 register enables the interrupt capability. The
four different rates available are a product of the MCU oscillator
frequency and the value of bits RTR[1:0]. Refer to Table 8-2, which
shows the periodic real-time interrupt rates.
Table 8-2. RTI periodic rates
RTR[1:0] E = 3MHz E = 2MHz E = 1MHz E = xMHz
213/E
0 0
0 1
1 0
1 1
2.731ms
5.461ms
4.096ms
8.192ms
8.192ms
16.384ms
214/E
215/E
216/E
10.923ms 16.384ms 32.768ms
21.845ms 32.768ms 65.536ms
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. This clock causes the time
between successive RTI timeouts to be a constant that is independent
of the software latency associated with flag clearing and service. For this
reason, an RTI period starts from the previous timeout, not from when
RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set,
an interrupt request is generated. After reset, one entire RTI period
elapses before the RTIF flag is set for the first time. Refer to the TMSK2,
TFLG2, and PACTL registers.
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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