Freescale Semiconductor, Inc.
Timing System
Output compare
I4/O5I — Input capture 4/output compare 5 interrupt enable
1 = IC4/OC5 interrupt is enabled.
0 = IC4/OC5 interrupt is disabled.
When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt
enable bit.
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt
enable bit.
IC1I–IC3I — Input capture x interrupt enable
1 = ICx interrupt is enabled.
0 = ICx interrupt is disabled.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware
interrupt sequence is requested.
8.5.8 TFLG1 — Timer interrupt flag register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Timer interrupt flag 1 (TFLG1) $0023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F 0000 0000
Bits in this register indicate when timer system events have occurred.
Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer
subsystem to operate in either a polled or interrupt driven system. Clear
flags by writing a one to the corresponding bit position(s).
NOTE: Bits in TFLG1 correspond bit for bit with flag bits in TMSK1. Ones in
TMSK1 enable the corresponding interrupt sources.
OC1F–OC4F — Output compare x flag
1 = Counter has reached the preset output compare x value.
0 = Counter has not reached the preset output compare x value.
These flags are set each time the counter matches the corresponding
output compare x values.
I4/O5F — Input capture 4/output compare 5 flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in
PACTL
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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