Freescale Semiconductor, Inc.
Motorola Interconnect Bus (MI BUS)
6.10.4 S2CR2 — MI BUS2 control register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
SCI/MI 2 control 2 (S2CR2)
$0053 TIE2 TCIE2 RIE2 ILIE2 TE2 RE2 RWU2 SBK2 0000 0000
RIE2 — Receiver interrupt enable 2
1 = MI BUS interrupt requested when RDRF2 flag is set.
0 = RDRF2 and OR2 interrupts disabled.
TE2 — Transmitter enable 2
1 = Transmitter enabled and port pin dedicated to the MI BUS.
0 = Transmitter disabled.
RE2 — Receiver enable 2
1 = Port pin dedicated to the MI BUS; the receiver is enabled by a
pull sync and is inhibited during a push field.
0 = Receiver disabled.
SBK2 — Send break 2
1 = MI transmit line is set low for 20 time slots.
0 = No action.
When an MI BUS wire is held low for eight or more time slots an
internal circuit on any slave device connected to the bus may reset or
preset the device with default values.
6.10.5 S2SR1 — MI BUS2 status register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2 NF2 FE2
SCI/MI 2 status 1 (S2SR1)
PF2 1100 0000
The bits in S2SR1 indicate certain conditions in the MI BUS hardware
and are automatically cleared by special acknowledge sequences. The
receive related flag bits in S2SR1 (RDRF2, OR2 and NF2) are cleared
by a read of this register followed by a read of the transmit/receive data
register. However, only those bits that were set when S2SR1 was read
will be cleared by the subsequent read of the transmit/receive data
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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