Freescale Semiconductor, Inc.
Motorola Interconnect Bus (MI BUS)
SCI/MI BUS2 registers
RDRF2 — Receive data register full flag 2
1 = Contents of the receiver serial shift register have been
transferred to the receiver data register.
0 = Contents of the receiver serial shift register have not been
transferred to the receiver data register.
This bit is set when the contents of the receiver serial shift register
have been transferred to the receiver data register.
The EOF (end-of-frame) during an MI BUS pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
– By clearing the RIE2 mask, ignoring unneeded RDRF2s,
initiating a push field, waiting for TDRE2(1) and then clearing
the RDRF2;
– By clearing the RE2 bit when a pull field is complete, followed
by setting the RE2 bit after the TDRE2† flag associated with
the next push field is asserted;
– By disabling the MI BUS.
OR2 — Bit error 2
1 = A bit error has been detected.
0 = No bit error has been detected.
This bit is set when a push field bit value on the MI BUS does not
match the bit value that was sent. This is known as an MI BUS bit
error. OR2 does not generate an interrupt request in MI BUS mode.
NF2 — Noise error flag 2
1 = Noise detected.
0 = No noise detected.
This bit is set when noise is detected on the receive line during an
MI BUS pull field.
1. Note that TDREx and TCx will both behave in the same way as during normal SCI transmis-
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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