Serial Host Interface (SHI) I2C Protocol Timing
SS
(Input)
143
141
147
142
144
144
144
SCK (CPOL = 0)
(Input)
146
142
144
143
SCK (CPOL = 1)
(Input)
152
152
153
151
150
MISO
(Output)
MSB
LSB
148
148
149
149
MSB
Valid
LSB
Valid
MOSI
(Input)
157
158
HREQ
(Output)
AA0274
Figure 3-30 SPI Slave Timing (CPHA = 1)
2
3.13 Serial Host Interface (SHI) I C Protocol Timing
Table 3-17 SHI I2C Protocol Timing
Standard I2C
Standard4, 5
Fast-Mode5, 6
Unit
Symbol/
Expression
No.
Characteristics1, 2, 3
Min
Max
Min
Max
Tolerable spike width on SCL or SDA
• Filters bypassed
—
ns
—
—
—
0
—
—
—
0
• Narrow filters enabled
• Wide filters enabled
50
50
100
100
171 SCL clock frequency
171 SCL clock cycle
FSCL
TSCL
—
10
100
—
—
400
—
kHz
µs
2.5
1.3
0.6
0.6
172 Bus free time
TBUF
4.7
4.7
4.0
—
—
µs
173 Start condition set-up time
174 Start condition hold time
TSU;STA
THD;STA
—
—
µs
—
—
µs
DSP56367 Technical Data, Rev. 2.1
3-42
Freescale Semiconductor
FREESCALE [ Freescale ]
