Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (continued)
Filter
Mode
No.
Characteristics1
Mode
Expression2
Min
Max
Unit
144 Serial clock rise/fall time
Master
Slave
—
—
—
—
—
—
10
ns
2000
146 SS assertion to first SCK edge
CPHA = 0
Slave
Slave
Slave
Bypassed
Narrow
Wide
3.5 × TC + 15
38.5
0
—
—
—
ns
ns
ns
ns
ns
0
0
0
CPHA = 1
Bypassed
Narrow
Wide
10
0
10
0
—
—
—
0
0
147 Last SCK edge to SS not asserted
Bypassed
Narrow
Wide
12
12
—
—
—
102
189
102
189
148 Data input valid to SCK edge (data input
set-up time)
Master/ Bypassed
Slave
0
0
—
—
—
Narrow
MAX{(20-TC), 0}
MAX{(40-TC), 0}
13.3
33.3
Wide
149 SCK last sampling edge to data input not Master/ Bypassed
2.5 × TC + 10
2.5 × TC + 30
2.5 × TC + 50
26.8
46.8
66.8
—
—
—
valid
Slave
Narrow
Wide
150 SS assertion to data out active
Slave
Slave
—
—
2
9
2
—
9
ns
ns
ns
151 SS deassertion to data high impedance3
—
152 SCK edge to data out valid (data out delay Master/ Bypassed
2 × TC + 33
2 × TC + 123
2 × TC + 210
—
—
—
46.4
136.4
223.4
time)
Slave
Narrow
Wide
153 SCK edge to data out not valid (data out
hold time)
Master/ Bypassed
TC + 5
TC + 55
TC + 106
11.7
61.7
—
—
—
ns
Slave
Narrow
Wide
112.7
154 SS assertion to data out valid (CPHA = 0) Slave
—
TC + 33
—
39.7
ns
ns
157 First SCK sampling edge to HREQ output Slave
deassertion
Bypassed
Narrow
Wide
2.5 × TC + 30
2.5 × TC + 120
2.5 × TC + 217
—
—
—
46.8
136.8
233.8
158 Last SCK sampling edge to HREQ output Slave
not deasserted (CPHA = 1)
Bypassed
Narrow
Wide
2.5 × TC + 30
2.5 × TC + 80
2.5 × TC + 136
46.8
96.8
—
—
—
ns
ns
152.8
159 SS deassertion to HREQ output not
deasserted (CPHA = 0)
Slave
—
2.5 × TC + 30
46.8
—
DSP56367 Technical Data, Rev. 2.1
3-38
Freescale Semiconductor
FREESCALE [ Freescale ]
