Serial Host Interface (SHI) I2C Protocol Timing
3.13.1 Programming the Serial Clock
2
The programmed serial clock cycle, T
HCKR (SHI clock control register).
, is specified by the value of the HDM[7:0] and HRS bits of the
I CCP
2
The expression for T
is
I CCP
T
= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
C
I2CCP
where
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is
operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256
(HDM[7:0] = $00 to $FF) may be selected.
2
In I C mode, the user may select a value for the programmed serial clock cycle from
6 × T (if HDM[7:0] = 02 and HRS = 1)
$
C
to
4096 × T (if HDM[7:0] =
$FF and HRS = 0)
C
2
The programmed serial clock cycle (T
), SCL rise time (T ), and the filters selected should be chosen
R
I CCP
in order to achieve the desired SCL serial clock cycle (T ), as shown in Table 3-18.
SCL
Table 3-18 SCL Serial Clock Cycle (TSCL) Generated as Master
2
Filters bypassed
T
T
T
+ 2.5 × TC + 45ns + T
I CCP
R
2
Narrow filters enabled
Wide filters enabled
+ 2.5 × TC + 135ns + T
+ 2.5 × TC + 223ns + T
I CCP
R
R
2
I CCP
EXAMPLE:
2
For DSP clock frequency of 100 MHz (i.e. T = 10ns), operating in a standard mode I C environment
C
(F
= 100 kHz (i.e. T
= 10µs), T = 1000ns), with wide filters enabled:
SCL
SCL R
T
= 10µs – 2.5 × 10ns – 223ns – 1000ns = 8752ns
I2CCP
Choosing HRS = 0 gives
HDM[7:0] = (8752ns) ⁄ (2 × 10ns × 8) – 1 = 53.7
Thus the HDM[7:0] value should be programmed to $36 (=54).
2
The resulting T
will be:
I CCP
T
= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – 0) + 1)]
C
I2CCP
T
= [10ns × 2 × (54 + 1) × (7 × (1 – 0) + 1)]
I2CCP
T
= [10ns × 2 × 54 × 8] = 8640ns
I2CCP
DSP56367 Technical Data, Rev. 2.1
3-44
Freescale Semiconductor
FREESCALE [ Freescale ]
