Enhanced Serial Audio Interface Timing
171
173
176
175
SCL
SDA
177
180
178
172
179
MSB
LSB
ACK
Stop
Stop
Start
174
188
186
182
183
187
189
184
HREQ
AA0275
Figure 3-31 I2C Timing
3.14 Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing1, 2
No.
Characteristics3, 4, 5
Symbol
Expression
Min
Max Condition6 Unit
430 Clock cycle7
tSSICC
4 × T
26.8
20.1
—
—
—
i ck
x ck
x ck
ns
C
3 × T
C
TXC:max[3*tc; 26.5
t454]
431 Clock high period
• For internal clock
• For external clock
—
—
ns
ns
2 × T − 10.0
3.4
—
—
C
1.5 × T
10.0
C
432 Clock low period
• For internal clock
• For external clock
2 × T − 10.0
3.4
—
—
C
1.5 × T
10.0
C
433 RXC rising edge to FSR out (bl) high
434 RXC rising edge to FSR out (bl) low
435 RXC rising edge to FSR out (wr) high8
436 RXC rising edge to FSR out (wr) low8
—
—
—
—
—
—
—
37.0
22.0
x ck
ns
ns
ns
ns
i ck a
—
—
—
—
—
37.0
22.0
x ck
i ck a
—
—
39.0
24.0
x ck
i ck a
—
—
39.0
24.0
x ck
i ck a
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-45
FREESCALE [ Freescale ]
