Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (continued)
Filter
Mode
No.
Characteristics1
Mode
Expression2
Min
Max
Unit
160 SS deassertion pulse width (CPHA = 0)
161 HREQ in assertion to first SCK edge
Slave
—
TC + 6
12.7
—
ns
ns
Master Bypassed 0.5 × tSPICC + 2.5 × TC + 43 97.8
—
—
—
Narrow
Wide
0.5 × tSPICC + 2.5 × TC + 43 160.8
0.5 × tSPICC + 2.5 × TC + 43 196.8
162 HREQ in deassertion to last SCK
sampling edge (HREQ in set-up time)
(CPHA = 1)
Master
Master
—
0
0
—
ns
ns
163 First SCK edge to HREQ in not asserted
(HREQ in hold time)
—
0
0
—
1
2
VCC = 1.8 V 5%; TJ = –40°C to +95°C, CL = 50 pF
The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit SHI testing to lower clock
frequencies.
3
Periodically sampled, not 100% tested
SS
(Input)
143
141
141
142
143
144
144
144
144
SCK (CPOL = 0)
(Output)
142
SCK (CPOL = 1)
(Output)
148
149
148
149
MISO
(Input)
MSB
Valid
LSB
Valid
153
152
MSB
MOSI
(Output)
LSB
161
163
HREQ
(Input)
AA0271
Figure 3-27 SPI Master Timing (CPHA = 0)
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-39
FREESCALE [ Freescale ]
