External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)
100 MHz
No.
Characteristics
Symbol
Expression3
Unit
Min
Max
—
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
tRWL
tCWL
tDS
15.75 × TC − 4.3
14.25 × TC − 4.3
8.75 × TC − 4.0
6.25 × TC − 4.0
9.75 × TC − 4.0
9.5 × TC − 4.3
1.5 × TC − 4.0
4.75 × TC − 4.0
15.5 × TC − 4.0
14 × TC − 5.7
153.2
138.2
83.5
58.5
93.5
90.7
11.0
43.5
151.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tDH
—
tDHR
tWCS
tCSR
tRPC
tROH
tGA
—
—
—
—
—
134.3
—
193 RD deassertion to data not valid5
194 WR assertion to data active
tGZ
0.0
0.75 × TC – 1.5
0.25 × TC
6.0
—
195 WR deassertion to data high impedance
—
2.5
1
2
3
4
5
The number of wait states for an out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
An expression is used to compute the maximum or minimum value listed (or both if the expression includes ).
Either tRCH or tRRH must be satisfied for read cycles.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
DSP56367 Technical Data, Rev. 2.1
3-26
Freescale Semiconductor
FREESCALE [ Freescale ]
