External Memory Expansion Port (Port A)
157
162
163
165
162
RAS
CAS
190
170
189
177
WR
AA0478
Figure 3-17 DRAM Refresh Access
3.10.3 Arbitration Timings
Table 3-14 Asynchronous Bus Arbitration Timing1, 2, 3
150 MHz
No.
Characteristics
Expression
Unit
Min
—
Max
21.7
—
250 BB assertion window from BG input negation.
251 Delay from BB assertion to BG assertion
2 .5* Tc + 5
2 * Tc + 5
ns
ns
18.3
1
2
3
Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode.
If Asynchronous Arbitration mode is active, none of the timings in Table 3-14 is required.
In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same
bus) in a non overlap manner as shown in Figure 3-18.
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-29
FREESCALE [ Freescale ]
