Specifications
CLKOUT
BR
212
214
213
BG
BB
219
218
221
A[0–23]
RD, WR
224
223
AA[0–3]
Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)
2.5.5.5 Asynchronous Bus Arbitrations Timings
Table 2-17. Asynchronous Bus Arbitration Timing1,3
80 MHz
100 MHz2
Min Max
No.
Characteristics
Expression
Unit
Min
Max
4
250
251
BB assertion window from BG input deassertion
2.5 × Tc + 5
2 × Tc + 5
—
25
—
—
30
ns
ns
4
Delay from BB assertion to BG assertion
25
25
—
Notes: 1. Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.
2. Asynchronous Arbitration mode is recommended for operation at 100 MHz.
3. If Asynchronous Arbitration mode is active, none of the timings in Table 2-16 is required.
4. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in
the non-overlap manner shown in Figure 2-26.
DSP56301 Technical Data, Rev. 10
2-32
Freescale Semiconductor
FREESCALE [ Freescale ]
