Specifications
Table 2-18. Universal Bus Mode Timing Parameters (Continued)
80 MHz
100 MHz
No.
Characteristic
Expression
Unit
Min Max
Min Max
313 Data Out Valid from Read Data Strobe Assertion
—
18.9
—
16.9
ns
3
(No Wait States Inserted—HTA Asserted)
314 Data Out Valid Hold from Read Data Strobe Deassertion
1.7
—
—
12.0
—
1.3
—
—
9.6
—
ns
ns
ns
ns
ns
ns
ns
3
3
315 Data Out High Impedance from Read Data Strobe Deassertion
4
316 Data In Valid Setup to Write Data Strobe Deassertion
8.3
0.0
—
6.6
0.0
—
4
317 Data In Valid Hold from Write Data Strobe Deassertion
—
—
1
318 HSAK Assertion from Data Strobe Assertion
30.0
—
30.0
—
1
319 HSAK Asserted Hold from Data Strobe Deassertion
2.0
3.1
38.0
2.0
2.5
1,2,5
320 HTA Active from Data Strobe Assertion
—
—
321 HTA Assertion from Data Strobe Assertion
80 MHz: 2.0 × T + 13.0
—
ns
ns
C
1,2,5
(HBS Not Used—Tied to V
)
100 MHz: 2.0 × T + 12.2
32.2
—
CC
C
2,5
322 HTA Assertion from HBS Assertion
80 MHz: 2.0 × T + 13.0
38.0
—
ns
ns
C
100 MHz: 2.0 × T + 12.2
32.2
—
—
15.0
—
C
1,2,5
323 HTA Deasserted from Data Strobe Assertion
—
0.0
—
17.1
—
ns
ns
ns
ns
ns
1,2
324 HTA Assertion to Data Strobe Deassertion
0.0
—
1,2
325 HTA High Impedance from Data Strobe Deassertion
326 HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
15.3
—
12.2
—
7
(LT + 1) × T − 6.0
19.0
0.0
14.0
0.0
C
327 Data Strobe Deasserted Hold from HIRQ Deassertion
—
—
1
(HIRH = 0)
1
328 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)
1.5 × T
18.8
—
—
15.0
—
—
ns
C
329 HIRQ Deassertion from Data Strobe Assertion
80 MHz: 2.5 × T + 24.7
100 MHz: 2.5 × T + 21.5
55.9
ns
ns
C
1
(HIRH = 1, HIRD = 1)
46.5
C
330 HIRQ High Impedance from Data Strobe Assertion
80 MHz: 2.5 × T + 24.7
—
55.9
—
ns
ns
C
1,6
(HIRH = 1, HIRD = 0)
100 MHz: 2.5 × T + 21.5
—
46.5
—
C
331 HIRQ Active from Data Strobe Deassertion
2.5 × T
31.3
25.0
ns
C
1
(HIRH = 1, HIRD = 0)
1
332 HIRQ Deasserted Hold from Data Strobe Deassertion
2.5 × T
31.3
18.8
—
—
—
25.0
15.0
—
—
ns
ns
C
2
1
333 HDRQ Asserted Hold from Data Strobe Assertion
1.5 × T
C
2
1
334 HDRQ Deassertion from Data Strobe Assertion
80 MHz: 2.5 × T + 24.7
100 MHz: 2.5 × T + 21.5
55.9
ns
ns
C
—
46.5
C
2
1
335 HDRQ Deasserted Hold from Data Strobe Deassertion
80 MHz: 2.5 × T + 3.7
35.0
—
ns
ns
C
100 MHz: 2.5 × T + 3.0
28.0
4.6
0.0
2.0
—
—
—
C
1
336 HDAK Assertion to Data Strobe Assertion
5.8
0.0
2.5
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
337 HDAK Asserted Hold from Data Strobe Deassertion
—
1
338 HDBEN Deasserted Hold from Data Strobe Assertion
—
—
1
339 HDBEN Assertion from Data Strobe Assertion
22.2
—
19.6
—
1
340 HDBEN Asserted Hold from Data Strobe Deassertion
2.5
—
2.0
—
1
341 HDBEN Deassertion from Data Strobe Deassertion
22.2
—
19.6
—
3
342 HDBDR High Hold from Read Data Strobe Assertion
2.5
—
2.0
—
3
343 HDBDR Low from Read Data Strobe Assertion
22.2
—
19.6
—
3
344 HDBDR Low Hold from Read Data Strobe Deassertion
2.5
2.0
DSP56301 Technical Data, Rev. 10
2-34
Freescale Semiconductor
FREESCALE [ Freescale ]
