Specifications
2.5.5.4 Arbitration Timings
Table 2-16. Arbitration Bus Timings1.
80 MHz
100 MHz
No.
Characteristics
Expression2
Unit
Min
Max
Min
Max
3
212
213
CLKOUT high to BR assertion/deassertion
1.0
5.0
4.5
—
0.0
4.0
4.0
—
ns
ns
BG asserted/deasserted to CLKOUT high
(setup)
214
CLKOUT high to BG deasserted/asserted
(hold)
0.0
—
0.0
—
ns
215
216
217
218
219
220
221
BB deassertion to CLKOUT high (input setup)
CLKOUT high to BB assertion (input hold)
CLKOUT high to BB assertion (output)
CLKOUT high to BB deassertion (output)
BB high to BB high impedance (output)
CLKOUT high to address and controls active
5.0
0.0
1.0
1.0
—
—
—
4.0
0.0
0.0
0.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
5.6
—
4.0
4.0
4.5
—
0.25 × T
3.1
—
2.5
—
C
CLKOUT high to address and controls high
impedance
0.75 × T
9.4
7.5
C
222
223
224
CLKOUT high to AA active
0.25 × T
3.1
4.1
—
—
2.5
2.0
—
—
ns
ns
ns
C
CLKOUT high to AA deassertion
CLKOUT high to AA high impedance
maximum: 0.25 × T + 4.0
7.1
9.4
6.5
7.5
C
0.75 × T
C
Notes: 1. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.
2. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an
absolute value.
3. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal
accesses and asserted for external accesses.
DSP56301 Technical Data, Rev. 10
2-30
Freescale Semiconductor
FREESCALE [ Freescale ]
