AC Electrical Characteristics
BG1
BB
250
BG2
251
250+251
Figure 2-26. Asynchronous Bus Arbitration Timing
The asynchronous bus arbitration is enabled by internal BB inputs and synchronization circuits on BG. These
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part can assume mastership and assert BB, for some time after BG is deasserted. Timing 250
defines when BB can be asserted.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other
DSP56300 components which are potential masters on the same bus. If BG input is asserted before that time, a
situation of BG asserted, and BB deasserted, can cause another DSP56300 component to assume mastership at the
same time. Therefore, a non-overlap period between one BG input active to another BG input active is required.
Timing 251 ensures that such a situation is avoided.
2.5.6 Host Interface Timing
Table 2-18. Universal Bus Mode Timing Parameters
80 MHz
100 MHz
No.
Characteristic
Expression
Unit
Min Max
Min Max
300 Access Cycle Time
3 × T
37.5
5.8
—
—
—
—
—
—
—
30.0
4.6
0.0
4.6
0.0
3.3
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
1
301 HA[10–0], HAEN Setup to Data Strobe Assertion
1
302 HA[10–0], HAEN Valid Hold from Data Strobe Deassertion
0.0
2
303 HRW Setup to HDS Assertion
5.8
2
304 HRW Valid Hold from HDS Deassertion
0.0
1
305 Data Strobe Deasserted Width
4.1
1
306 Data Strobe Asserted Pulse Width
80 MHz: 2.5 × T + 1.7
100 MHz: 2.5 × T + 1.3
32.9
ns
ns
C
26.3
2.0
—
—
C
307 HBS Asserted Pulse Width
2.5
—
—
ns
1
308 HBS Assertion to Data Strobe Assertion
80 MHz: T − 4.9
7.6
ns
ns
C
100 MHz: T − 4.0
—
6.0
—
C
1
309 HBS Assertion to Data Strobe Deassertion
80 MHz: 2.5 × T + 2.9
100 MHz: 2.5 × T + 2.3
34.1
22.1
13.4
1.7
—
—
—
—
ns
ns
C
27.3
17.6
C
1
310 HBS Deassertion to Data Strobe Deassertion
80 MHz: 1.5 × T + 3.3
100 MHz: 1.5 × T + 2.6
ns
ns
C
—
C
2
311 Data Out Valid to TA Assertion (HBS Not Used—Tied to V
)
80 MHz: 2 × T − 11.6
100 MHz: 2 × T − 9.2
ns
ns
CC
C
10.8
1.3
—
—
C
3
312 Data Out Active from Read Data Strobe Assertion
ns
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-33
FREESCALE [ Freescale ]
